{"id":5571,"date":"2026-02-04T07:31:47","date_gmt":"2026-02-04T07:31:47","guid":{"rendered":"https:\/\/cephasconsult.biz\/?post_type=job_listing&p=5571"},"modified":"2026-03-07T00:16:47","modified_gmt":"2026-03-07T00:16:47","slug":"sr-layout-designer-46392","status":"expired","type":"job_listing","link":"https:\/\/cephasconsult.biz\/?post_type=job_listing&p=5571","title":{"rendered":"Sr. Layout Designer 46392"},"content":{"rendered":"

Positions:1 <\/span><\/span>Full Time<\/span><\/p>\n

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Experience<\/div>\n
10 – 15 Years<\/div>\n
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Compensation Details<\/div>\n
Meaningful Equity<\/div>\n<\/div>\n
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Key Responsibilities<\/strong><\/h2>\n
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  • Own the physical layout design of high-performance ADC\/DAC, SerDes, and analog\/mixed-signal circuits across advanced nodes (2nm\u201316nm).<\/li>\n
  • Plan, and implement layout design for high-speed, low-noise analog blocks, ensuring signal integrity, matching, symmetry, and optimal parasitics.<\/li>\n
  • Closely \u00a0<\/span>Collaborate \u00a0<\/span>with circuit designers to achieve aggressive power, performance, and area (PPA) targets, while maintaining design-for-manufacturability (DFM) best practices.<\/li>\n
  • Work with Cadence Virtuoso and Synopsys Verification \u00a0<\/span>tools to perform layout design, verification, and integration.<\/li>\n
  • Drive floorplanning and analog block partitioning, ensuring effective power grid design, guard ring placement, and substrate isolation techniques.<\/li>\n
  • Partner with foundry and CAD teams to optimize design flows for TSMC FinFET and Gate-All-Around (GAA) process nodes.<\/li>\n
  • Conduct LVS, DRC, ERC, and parasitic extraction (PEX) reviews and close layout verification loops.<\/li>\n
  • Participate in top-level integration and tape-out, ensuring all layout data and GDS handoffs meet signoff requirements.<\/li>\n
  • Provide technical mentorship to fellow engineers and help define layout design methodologies and automation improvements.<\/li>\n<\/ul>\n

    Minimum Qualifications<\/strong><\/h2>\n
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    • 10+ years of industry experience in analog\/mixed-signal layout design in advanced process nodes (2nm\u201316nm, preferably TSMC).<\/li>\n
    • Proven track record designing layouts for high-speed ADC\/DAC and SerDes circuits, with deep understanding of timing, matching, shielding, and electromigration considerations.<\/li>\n
    • Hands-on experience with Cadence Virtuoso tools (Layout, XL, PVS, Quantus) and solid understanding of schematic-to-layout (S2L) flow.<\/li>\n
    • Experience with FinFET and\/or Gate-All-Around (GAA) process technologies.<\/li>\n
    • Strong understanding of analog layout techniques: current mirrors, differential pairs, resistors, capacitors, biasing, shielding, guard rings, and ESD structures.<\/li>\n
    • Experience leading tape-outs, including design documentation, sign-off checks, and cross-team coordination.<\/li>\n
    • Strong analytical, problem-solving, and communication skills.<\/li>\n
    • \u00a0<\/span><\/li>\n<\/ul>\n

      Preferred Qualifications<\/strong><\/h2>\n
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      • Familiarity with Mentor\/Siemens Calibre<\/strong> verification tools and scripting (Skill, Python, or Tcl) for layout automation.<\/li>\n
      • Exposure to floorplanning and top-level chip integration<\/strong> for complex mixed-signal SoCs.<\/li>\n
      • Experience optimizing for signal integrity, IR drop, and thermal effects<\/strong> in high-speed designs.<\/li>\n<\/ul>\n

        Why Join US<\/strong><\/h2>\n
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        • Join a world-class analog\/mixed-signal design team<\/strong> building next-generation\u00a0 <\/span>cutting-edge ADC\/DAC and SerDes solutions<\/strong> in advanced CMOS and FinFET technologies<\/strong> for optical communication and high-speed data interfaces<\/strong>.<\/li>\n
        • <\/li>\n
        • Work hands-on with TSMC\u2019s most advanced process nodes<\/strong> (FinFET & GAA) and directly impact high-volume, high-speed products.<\/li>\n
        • Contribute across the entire silicon lifecycle<\/strong> \u2014 from floorplanning to tape-out \u2014 in a culture that values technical excellence and ownership<\/strong>.<\/li>\n
        • Competitive compensation, equity participation, and a collaborative environment where innovation drives outcomes.<\/li>\n<\/ul>\n<\/div>\n","protected":false},"author":1,"featured_media":0,"template":"","meta":{"_job_location":"Austin, Texas, USA","_application":"hrm@cephasconsult.biz","_company_name":"","_company_website":"","_company_tagline":"","_company_twitter":"","_company_video":"","_filled":0,"_featured":0,"_remote_position":0,"_job_salary":"","_job_salary_currency":"","_job_salary_unit":""},"job-types":[],"class_list":["post-5571","job_listing","type-job_listing","status-expired","hentry"],"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/cephasconsult.biz\/index.php\/wp-json\/wp\/v2\/job-listings\/5571","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/cephasconsult.biz\/index.php\/wp-json\/wp\/v2\/job-listings"}],"about":[{"href":"https:\/\/cephasconsult.biz\/index.php\/wp-json\/wp\/v2\/types\/job_listing"}],"author":[{"embeddable":true,"href":"https:\/\/cephasconsult.biz\/index.php\/wp-json\/wp\/v2\/users\/1"}],"wp:attachment":[{"href":"https:\/\/cephasconsult.biz\/index.php\/wp-json\/wp\/v2\/media?parent=5571"}],"wp:term":[{"taxonomy":"job_listing_type","embeddable":true,"href":"https:\/\/cephasconsult.biz\/index.php\/wp-json\/wp\/v2\/job-types?post=5571"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}