{"id":5888,"date":"2026-04-18T04:53:11","date_gmt":"2026-04-18T04:53:11","guid":{"rendered":"https:\/\/cephasconsult.biz\/?post_type=job_listing&p=5888"},"modified":"2026-05-19T00:15:56","modified_gmt":"2026-05-19T00:15:56","slug":"design-engineer-217","status":"expired","type":"job_listing","link":"https:\/\/cephasconsult.biz\/?post_type=job_listing&p=5888","title":{"rendered":"Design Engineer 217"},"content":{"rendered":"

Experience<\/p>\n

2 yrs – 15 yrs<\/p>\n

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Job Overview<\/h4>\n
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Openings<\/p>\n

8<\/p>\n<\/div>\n<\/div>\n

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Preferred Industries<\/p>\n

IT<\/p>\n<\/div>\n<\/div>\n

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Relevant Experience<\/p>\n

2 yrs – 15 yrs<\/p>\n<\/div>\n<\/div>\n

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Employment Type<\/p>\n

Full Time<\/p>\n<\/div>\n<\/div>\n

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Work Type<\/p>\n

Remote<\/p>\n<\/div>\n<\/div>\n

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Annual CTC<\/p>\n<\/div>\n<\/div>\n

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Gender<\/p>\n

Any<\/p>\n<\/div>\n<\/div>\n

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Qualification<\/p>\n

Graduate<\/p>\n<\/div>\n<\/div>\n

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Notice Period<\/p>\n

Immediate – 30 days<\/p>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/section>\n

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Job Description<\/h4>\n
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Job Title: Design Engineer (Remote)<\/u><\/strong><\/h3>\n

We are looking for candidates who worked on developing ASIC chips and\/or FPGAs. Design experience or design verification experience, or both. Chip architecture knowledge is also relevant.<\/p>\n

The job responsibilities would look roughly as follows:<\/strong><\/p>\n

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  • Design, implement, and verify RTL modules (SystemVerilog or Verilog)<\/li>\n
  • Convert existing hardware IP, including open-source repositories, into structured homework problems (i.e., \u201ctake this existing implementation of a communication protocol and modify it to send 3 data packets instead of 2\u201d)<\/li>\n
  • Define realistic homework problems that have clear learning objectives and align with industry complexity and use-cases<\/li>\n
  • Debug module-level and soc-level hardware behavior<\/li>\n
  • Work autonomously in a fast-paced environment without needing significant oversight<\/li>\n<\/ul>\n

    Skills and Qualifications:<\/strong><\/p>\n

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    • Strong coding ability in systemerilog \/ verilog (required)<\/li>\n
    • Experience in RTL design and\/or RTL design verification<\/li>\n
    • Solid understanding of digital design fundamentals, simulation flows, and verification methodologies.<\/li>\n
    • Ability to communicate low-level hardware concepts clearly to non-hardware stakeholders.<\/li>\n
    • Strong English speaking and writing skills<\/li>\n<\/ul>\n

      Nice-to-haves:<\/strong><\/p>\n

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      • Previous experience contributing to a production ASIC chip<\/li>\n
      • Exposure to AI\/LLM engineering tools (e.g. ChatGPT, Copilot, Claude, etc.)<\/li>\n
      • Prior work in startups or fast-scaling engineering teams<\/li>\n<\/ul>\n<\/div>\n<\/div>\n<\/section>\n","protected":false},"author":1,"featured_media":0,"template":"","meta":{"_job_location":"","_application":"hrm@cephasconsult.biz","_company_name":"","_company_website":"","_company_tagline":"","_company_twitter":"","_company_video":"","_filled":0,"_featured":0,"_remote_position":1,"_job_salary":"","_job_salary_currency":"","_job_salary_unit":""},"job-types":[],"class_list":["post-5888","job_listing","type-job_listing","status-expired","hentry"],"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/cephasconsult.biz\/index.php\/wp-json\/wp\/v2\/job-listings\/5888","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/cephasconsult.biz\/index.php\/wp-json\/wp\/v2\/job-listings"}],"about":[{"href":"https:\/\/cephasconsult.biz\/index.php\/wp-json\/wp\/v2\/types\/job_listing"}],"author":[{"embeddable":true,"href":"https:\/\/cephasconsult.biz\/index.php\/wp-json\/wp\/v2\/users\/1"}],"wp:attachment":[{"href":"https:\/\/cephasconsult.biz\/index.php\/wp-json\/wp\/v2\/media?parent=5888"}],"wp:term":[{"taxonomy":"job_listing_type","embeddable":true,"href":"https:\/\/cephasconsult.biz\/index.php\/wp-json\/wp\/v2\/job-types?post=5888"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}